? semiconductor components industries, llc, 2004 march, 2004 ? rev. 4 1 publication order number: mtd20p06hdl/d mtd20p06hdl preferred device power mosfet 20 amps, 60 volts, logic level p?channel dpak this power mosfet is designed to withstand high energy in the avalanche and commutation modes. the energy efficient design also offers a drain?to?source diode with a fast recovery time. designed for low?voltage, high?speed switching applications in power supplies, converters and pwm motor controls, and other inductive loads. the avalanche energy capability is specified to eliminate the guesswork in designs where inductive loads are switched, and to offer additional safety margin against unexpected voltage transients. ? ultra low r ds(on) , high?cell density, hdtmos ? diode is characterized for use in bridge circuits ? i dss and v ds(on) specified at elevated temperature ? avalanche energy specified maximum ratings (t c = 25 c unless otherwise noted) rating symbol value unit drain?source voltage v dss 60 vdc drain?gate voltage (r gs = 1.0 m ) v dgr 60 vdc gate?source voltage ? continuous ? non?repetitive (t p 10 ms) v gs v gsm 15 20 vdc vpk drain current ? continuous ? continuous @ 100 c ? single pulse (t p 10 s) i d i d i dm 15 9.0 45 adc apk total power dissipation derate above 25 c total power dissipation @ t c = 25 c (note 2) p d 72 0.58 1.75 watts w/ c watts operating and storage temperature range t j , t stg ?55 to 150 c single pulse drain?to?source avalanche energy ? starting t j = 25 c (v dd = 25 vdc, v gs = 5.0 vdc, i l = 15 apk, l = 2.7 mh, r g = 25 ) e as 300 mj thermal resistance ? junction?to?case ? junction?to?ambient (note 1) ? junction?to?ambient (note 2) r jc r ja r ja 1.73 100 71.4 c/w maximum lead temperature for soldering purposes, 1/8 from case for 10 seconds t l 260 c 1. when surface mounted to an fr4 board using the minimum recommended pad size. 2. when surface mounted to an fr4 board using 0.5 sq. inch pad size. 1 gate 3 source 2 drain 4 drain d s g 20 amperes 60 volts r ds(on) = 175 m device package shipping 2 ordering information mtd20p06hdl dpak 75 units/rail dpak case 369c (surface mount) style 2 p?channel marking diagram 20p06hl = device code y = year ww = work week MTD20P06HDLT4 dpak 2500 tape & reel preferred devices are recommended choices for future use and best overall value. http://onsemi.com 1 2 3 4 yww 20p 06hl 2for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d.
mtd20p06hdl http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics drain?source breakdown voltage (v gs = 0 vdc, i d = 250 adc) temperature coefficient (positive) v (br)dss 60 ? ? 81.3 ? ? vdc mv/ c zero gate voltage drain current (v ds = 60 vdc, v gs = 0 vdc) (v ds = 60 vdc, v gs = 0 vdc, t j = 125 c) i dss ? ? ? ? 1.0 10 adc gate?body leakage current (v gs = 15 vdc, v ds = 0) i gss ? ? 100 nadc on characteristics (note 3) gate threshold voltage (v ds = v gs , i d = 250 adc) temperature coefficient (negative) v gs(th) 1.0 ? 1.7 3.9 2.0 ? vdc mv/ c static drain?source on?resistance (v gs = 5.0 vdc, i d = 7.5 adc) r ds(on) ? 143 175 m drain?source on?voltage (v gs = 5.0 vdc) (i d = 15 adc) (i d = 7.5 adc, t j = 125 c) v ds(on) ? ? 2.3 1.6 3.0 2.0 vdc forward transconductance (v ds = 10 vdc, i d = 7.5 adc) g fs 9.0 11 ? mhos dynamic characteristics input capacitance c iss ? 850 1190 pf output capacitance (v ds = 25 vdc, v gs = 0 vdc, f = 1.0 mhz ) c oss ? 210 290 reverse transfer capacitance f = 1 . 0 mhz) c rss ? 66 130 switching characteristics (note 4) turn?on delay time t d(on) ? 19 38 ns rise time (v ds = 30 vdc, i d = 15 adc, v gs =50vdc t r ? 175 350 turn?off delay time v gs = 5.0 vdc, r g = 9.1 ) t d(off) ? 41 82 fall time g ) t f ? 68 136 gate charge q t ? 20.6 29 nc (v d s = 48 vdc, i d = 15 adc, q 1 ? 3.7 ? (v ds = 48 vdc , i d = 15 adc , v gs = 5.0 vdc) q 2 ? 7.6 ? q 3 ? 8.4 ? source?drain diode characteristics forward on?voltage (i s = 15 adc, v gs = 0 vdc) (i s = 15 adc, v gs = 0 vdc, t j = 125 c) v sd ? ? 2.5 1.9 3.0 ? vdc reverse recovery time t rr ? 64 ? ns ( i s = 15 adc, v gs = 0 vdc, t a ? 50 ? (i s = 15 adc , v gs = 0 vdc , di s /dt = 100 a/ s) t b ? 14 ? reverse recovery stored charge q rr ? 0.177 ? c internal package inductance internal drain inductance (measured from the drain lead 0.25 from package to center of die) l d ? 4.5 ? nh internal source inductance (measured from the source lead 0.25 from package to source bond pad) l s ? 7.5 ? nh 3. pulse test: pulse width 300 s, duty cycle 2%. 4. switching characteristics are independent of operating junction temperature.
mtd20p06hdl http://onsemi.com 3 typical electrical characteristics r ds(on) , drain-to-source resistance (ohms) r ds(on) , drain-to-source resistance (normalized) r ds(on) , drain-to-source resistance (ohms) i dss , leakage (na) v ds , drain-to-source voltage (volts) t j , junction temperature ( c) i d , drain current (amps) i d , drain current (amps) v ds , drain-to-source voltage (volts) v gs , gate-to-source voltage (volts) i d , drain current (amps) i d , drain current (amps) 03 25 14 figure 1. on?region characteristics figure 2. transfer characteristics 0102030 figure 3. on?resistance versus drain current and temperature figure 4. on?resistance versus drain current and gate voltage 1 100 figure 5. on?resistance variation with temperature figure 6. drain?to?source leakage current versus voltage 13 56 v ds 5 v 100 c 25 c v gs = 5 v -55 c 25 c 030 -50 -25 0 25 50 75 100 125 150 0 10 20 60 40 v gs = 0 v t j = 125 c t j = 100 c t j = 25 c v gs = 5 v v gs = 5 v i d = 7.5 a 24 10 50 30 v gs = 10 v 8 v 4 v t j = 25 c 100 c 515 15 25 10 25 520 10 v 30 25 20 15 10 5 0 8 710 69 6 v 7 v 9 v 30 25 20 15 10 5 0 t j = -55 c 0.40 0.32 0.24 0.16 0.08 0 0.275 0.250 0.225 0.200 0.175 0.150 0.125 0.100 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 5 v
mtd20p06hdl http://onsemi.com 4 power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge controlled. the lengths of various switching intervals ( t) are determined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is difficult to use for calculating rise and fall because drain?gate capacitance varies greatly with applied voltage. accordingly, gate charge data is used. in most cases, a satisfactory estimate of average input current (i g(av) ) can be made from a rudimentary analysis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resistive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg ? v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turn?on and turn?off delay times, gate current is not constant. the simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg ? v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the off?state condition when calculating t d(on) and is read at a voltage corresponding to the on?state when calculating t d(off) . at high switching speeds, parasitic circuit elements complicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. the mosfet output capacitance also complicates the mathematics. and finally, mosfets have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. the resistive switching time variation versus gate resistance (figure 9) shows how typical switching performance is affected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. power mosfets may be safely operated into an inductive load; however, snubbing reduces switching losses. gate-to-source or drain-to-source voltage (volts) c, capacitance (pf) figure 7. capacitance variation 10 0 10 15 20 25 2500 2000 500 0 v gs v ds 1500 1000 55 v ds = 0 v c iss c rss v gs = 0 v t j = 25 c c iss c oss c rss
mtd20p06hdl http://onsemi.com 5 q g , total gate charge (nc) r g , gate resistance (ohms) t, time (ns) v ds , drain-to-source voltage (volts) v gs , gate-to-source voltage (volts) figure 8. gate?to?source and drain?to?source voltage versus total charge 1 100 1000 1 100 v dd = 30 v i d = 15 a v gs = 5.0 v t j = 25 c t r t f t d(on) t d(off) figure 9. resistive switching time variation versus gate resistance 048 16 24 12 3 1 0 4 2 6 50 40 35 30 20 25 0 v gs i d = 15 a t j = 25 c v ds q3 q1 45 5 20 qt q2 10 10 15 10 5 drain?to?source diode characteristics the switching characteristics of a mosfet body diode are very important in systems using it as a freewheeling or commutating diode. of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, emi and rfi. system switching losses are largely due to the nature of the body diode itself. the body diode is a minority carrier device, therefore it has a finite reverse recovery time, t rr , due to the storage of minority carrier charge, q rr , as shown in the typical reverse recovery wave form of figure 12. it is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. therefore, one would like a diode with short t rr and low q rr specifications to minimize these losses. the abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. the mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by high di/dts. the diode's negative di/dt during t a is directly controlled by the device clearing the stored charge. however, the positive di/dt during t b is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. therefore, when comparing diodes, the ratio of t b /t a serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. a ratio of 1 is considered ideal and values less than 0.5 are considered snappy. compared to on semiconductor standard cell density low voltage mosfets, high cell density mosfet diodes are faster (shorter t rr ), have less stored charge and a softer reverse recovery characteristic. the softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell mosfet diode without increasing the current ringing or the noise generated. in addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. i s , source current (amps) v sd , source-to-drain voltage (volts) 0.5 1.5 figure 10. diode forward voltage versus current 1 v gs = 0 v t j = 25 c 2.5 1.25 2 0.75 1.75 2.25 15 12 9 6 3 0
mtd20p06hdl http://onsemi.com 6 i s , source current t, time figure 11. reverse recovery time (t rr ) di/dt = 300 a/ s standard cell density high cell density t b t rr t a t rr safe operating area the forward biased safe operating area curves define the maximum simultaneous drain?to?source voltage and drain current that a transistor can handle safely when it is forward biased. curves are based upon maximum peak junction temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, atransient thermal resistance ? general data and its use.o switching between the off?state and the on?state may traverse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded, and that the transition time (t r , t f ) does not exceed 10 s. in addition the total power averaged over a complete switching cycle must not exceed (t j(max) ? t c )/(r jc ). a power mosfet designated e?fet can be safely used in switching circuits with unclamped inductive loads. for reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. the energy rating decreases non?linearly with an increase of peak current in avalanche and peak junction temperature. although many e?fets can withstand the stress of drain?to?source avalanche at currents up to rated pulsed current (i dm ), the energy rating is specified at rated continuous current (i d ), in accordance with industry custom. the energy rating must be derated for temperature as shown in the accompanying graph (figure 13). maximum energy at currents below rated continuous i d can safely be assumed to equal the values indicated. v ds , drain-to-source voltage (volts) i d , drain current (amps) e as , single pulse drain-to-source avalanche energy (mj) t j , starting junction temperature ( c) figure 12. maximum rated forward biased safe operating area 0 25 50 75 100 125 180 300 60 120 150 240 0.1 1.0 100 100 1.0 0.1 10 figure 13. maximum avalanche energy versus starting junction temperature 10 100 s 1 ms 10 ms i d = 15 a v gs = 20 v single pulse t c = 25 c r ds(on) limit thermal limit package limit dc
mtd20p06hdl http://onsemi.com 7 typical electrical characteristics d = 0.5 0.05 0.01 single pulse r jc (t) = r(t) r jc d curves apply for power pulse train shown read time at t 1 t j(pk) - t c = p (pk) r jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 r(t), effective transient thermal resistance (normalized) 0.1 1.0 0.01 figure 14. thermal response t, time (s) figure 15. diode reverse recovery waveform di/dt t rr t a t p i s 0.25 i s time i s t b 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 1.0e+00 1.0e+01 0.1 0.02 0.2
mtd20p06hdl http://onsemi.com 8 package dimensions dpak case 369c?01 issue o d a k b r v s f l g 2 pl m 0.13 (0.005) t e c u j h ?t? seating plane z dim min max min max millimeters inches a 0.235 0.245 5.97 6.22 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.018 0.023 0.46 0.58 f 0.037 0.045 0.94 1.14 g 0.180 bsc 4.58 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.102 0.114 2.60 2.89 l 0.090 bsc 2.29 bsc r 0.180 0.215 4.57 5.45 s 0.025 0.040 0.63 1.01 u 0.020 ??? 0.51 ??? v 0.035 0.050 0.89 1.27 z 0.155 ??? 3.93 ??? 123 4 style 2: pin 1. gate 2. drain 3. source 4. drain 5.80 0.228 2.58 0.101 1.6 0.063 6.20 0.244 3.0 0.118 6.172 0.243 mm inches scale 3:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 mtd20p06hdl/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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